1 Stück Design Tools for Security Chiplets (FMD-AISEC-Design-11.1/11.3) For the development of demanding analog and high complex digital circuits with advanced requirements in chiplet design in nanometer silicon technologies a backend tool suite will be needed by Fraunhofer matching and complementing the existing tool family. An analog and digital backend chip design software will be required for the development of high complex and high performance chiplets from netlist and schematic to GDSII chip layouts in tiny nanometer technologies. This request for proposal covers a full chip and block level constraint checker and clock domain crossing signoff tool including several digital functional simulators.